View LSM6DS0_9053254.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. november 2014 docid025604 rev 3 1/59 LSM6DS0 inemo inertial module: 3d accelerometer and 3d gyroscope datasheet - production data features ? analog supply voltage: 1.71 v to 3.6 v ? independent ios supply (1.71 v) ? ?always on? eco power mode down to 1.8 ma ? 3 independent acceleration channels and 3 angular rate channels ? 2/4/8/16 g full scale ? 245/500/2000 dps full scale ? spi/i 2 c serial interface ? embedded temperature sensor ? embedded fifo ? ecopack ? , rohs and ?green? compliant applications ? gps navigation systems ? impact recognition and logging ? gaming and virtual reality input devices ? motion-activated functions ? intelligent power saving for handheld devices ? vibration monitoring and compensation ? free-fall detection ? 6d orientation detection description the LSM6DS0 is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope. st?s family of mems sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are developed using cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the LSM6DS0 has a full-scale acceleration range of 2/4/8/16 g and an angular rate range of 245/500/2000 dps. the LSM6DS0 has two operating modes in that the accelerometer and gyroscope sensors can be either activated at the same odr or the accelerometer can be enabled while the gyroscope is in power-down. the LSM6DS0 is available in a plastic land grid array (lga) package. lga-16l (3x3x0.86 mm) table 1. device summary part number temp. range [c] package packing LSM6DS0 -40 to +85 lga-16l (3x3x0.86 mm) tray LSM6DS0tr -40 to +85 tape and reel www.st.com
contents LSM6DS0 2/59 docid025604 rev 3 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.2 zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 multiple reads (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 digital block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.3 continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.4 continuous-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.5 bypass-to-continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid025604 rev 3 3/59 LSM6DS0 contents 59 4.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 act_ths (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 act_dur (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 int_gen_cfg_xl (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 int_gen_ths_x_xl (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 int_gen_ths_y_xl (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6 int_gen_ths_z_xl (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 int_gen_dur_xl (0ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.8 reference_g (0bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.9 int_ctrl (0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.11 ctrl_reg1_g (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.12 ctrl_reg2_g (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.13 ctrl_reg3_g (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.14 orient_cfg_g (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.15 int_gen_src_g (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.16 out_temp_l (15h), out_temp_h (16h) . . . . . . . . . . . . . . . . . . . . . . . 43 7.17 status_reg (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.18 out_x_g (18h - 19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.19 out_y_g (1ah - 1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.20 out_z_g (1ch - 1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.21 ctrl_reg4 (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.22 ctrl_reg5_xl (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.23 ctrl_reg6_xl (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.24 ctrl_reg7_xl (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.25 ctrl_reg8 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.26 ctrl_reg9 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
contents LSM6DS0 4/59 docid025604 rev 3 7.27 ctrl_reg10 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.28 int_gen_src_xl (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.29 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.30 out_x_xl (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.31 out_y_xl (2ah - 2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.32 out_z_xl (2ch - 2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.33 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.34 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.35 int_gen_cfg_g (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.36 int_gen_ths_x_g (31h - 32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.37 int_gen_ths_y_g (33h - 34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.38 int_gen_ths_z_g (35h - 36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.39 int_gen_dur_g (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
docid025604 rev 3 5/59 LSM6DS0 list of tables 59 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. gyroscope operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 10. operating mode current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. accelerometer turn-on time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. gyroscope turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 15. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 28 table 19. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 28 table 20. register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 21. act_ths register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 22. act_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 23. act_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 24. act_dur register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 25. int_gen_cfg_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 26. int_gen_cfg_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 27. int_gen_ths_x_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 28. int_gen_ths_x_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 29. int_gen_ths_y_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 30. int_gen_ths_y_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 31. int_gen_ths_z_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 table 32. int_gen_ths_z_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 33. int_gen_dur_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 34. int_gen_dur_xl register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 35. reference_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 36. reference_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 37. int_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 38. int_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 39. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 40. ctrl_reg1_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 41. ctrl_reg1_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 42. odr and bw configuration setting (after lpf1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 43. odr and bw configuration setting (after lpf2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 44. ctrl_reg2_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 45. ctrl_reg2_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 46. ctrl_reg3_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 47. ctrl_reg3_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 48. gyroscope high-pass filter cutoff frequency configuration [hz]. . . . . . . . . . . . . . . . . . . . . . 42
list of tables LSM6DS0 6/59 docid025604 rev 3 table 49. orient_cfg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 50. orient_cfg_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 51. int_gen_src_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 52. int_gen_src_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 53. out_temp_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 54. out_temp_h register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 55. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 56. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 57. status_reg register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 58. ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 59. ctrl_reg4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 table 60. ctrl_reg5_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 61. ctrl_reg5_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 62. ctrl_reg6_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 63. ctrl_reg6_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 64. odr register setting (accelerometer only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 65. ctrl_reg7_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 66. ctrl_reg7_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 67. low pass cut-off frequency in high resolution mode (hr = 1) . . . . . . . . . . . . . . . . . . . . . . 47 table 68. ctrl_reg8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 69. ctrl_reg8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 table 70. ctrl_reg9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 71. ctrl_reg9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 table 72. ctrl_reg10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 73. ctrl_reg10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 74. int_gen_src_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 75. int_gen_src_xl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 76. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 77. status_reg register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 78. fifo_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 79. fifo_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 80. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 81. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 82. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 83. fifo_src example: ovr/fss details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 84. int_gen_cfg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 85. int_gen_cfg_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 86. int_gen_ths_xh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 87. int_gen_ths_xl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 88. int_gen_ths_x_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 89. int_gen_ths_yh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 90. int_gen_ths_yl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 91. int_gen_ths_y_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 92. int_gen_ths_zh_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 93. int_gen_ths_zl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 94. int_gen_ths_z_g register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 95. int_gen_dur_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 96. int_gen_dur_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 97. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
docid025604 rev 3 7/59 LSM6DS0 list of figures 59 list of figures figure 1. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. i 2 c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. switching operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. multiple reads: accelerometer only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 7. multiple reads: accelerometer and gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. digital block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. continuous-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. bypass-to-continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20. LSM6DS0 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 21. int_sel and out_sel configuration gyroscope block diagram . . . . . . . . . . . . . . . . . . . 41 figure 22. wait bit disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 23. wait bit enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 24. lga 3x3x0.86 16l package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
pin description LSM6DS0 8/59 docid025604 rev 3 1 pin description figure 1. pin connections (top view) directions of the detectable angular rates x z x y (top view) direction of the detectable accelerations y x z vdd_io scl/spc sda/sdi/sdo sdo/sa0 res int res cs res cap res vdd 1 8 6 16 bottom view 5 13 9 res res gnd gnd 14 + + +
docid025604 rev 3 9/59 LSM6DS0 pin description 59 table 2. pin description pin# name function 1 vdd_io (1) 1. recommended 100 nf filter capacitor. power supply for i/o pins 2 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 3 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 sdo sa0 spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 5cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 6 res leave unconnected 7 int programmable interrupt 8 res connect to gnd 9 res connect to gnd 10 res connect to gnd 11 res connect to vdd or gnd 12 gnd 0 v supply 13 gnd 0 v supply 14 cap connect to gnd with ceramic capacitor (2) 2. 10 nf (10%), 16 v. 1 nf minimum value has to be guaranteed under 11 v bias condition. 15 res connect to vdd or gnd 16 vdd (3) 3. recommended 100 nf plus 10 f capacitors. power supply
module specifications LSM6DS0 10/59 docid025604 rev 3 2 module specifications 2.1 mechanical characteristics @ vdd = 2.2 v, t = 25 c unless otherwise noted (a) a. the product is factory calibrated at 2.2 v. the operational power supply range is from 1.71 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range 2 g 4 8 16 g_fs angular rate measurement range 245 dps 500 2000 la_so linear acceleration sensitivity fs = 2 g 0.061 mg/lsb fs = 4 g 0.122 fs = 8 g 0.244 fs = 16 g 0.732 g_so angular rate sensitivity fs = 245 dps 8.75 mdps/lsb fs = 500 dps 17.50 fs = 2000 dps 70 la_tyoff linear acceleration typical zero- g level offset accuracy (2) fs = 8 g 90 m g g_tyoff angular rate typical zero-rate level (3) fs = 2000 dps 30 dps la_odr linear acceleration output data rate gyro on 952 476 238 119 59.5 14.9 hz gyro off 952 476 238 119 50 10 hz
docid025604 rev 3 11/59 LSM6DS0 module specifications 59 g_odr angular digital output data rate 952 476 238 119 59.5 14.9 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. typical zero-g level offset value after soldering. 3. typical zero-rate level offset value after msl3 preconditioning. table 3. mechanical characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit
module specifications LSM6DS0 12/59 docid025604 rev 3 2.2 electrical characteristics @ vdd = 2.2 v, t = 25 c unless otherwise noted table 4. electrical characteristics 2.2.1 recommended power-up sequence for the power-up sequence please refer to the following figure, where: ? trise is the time for the power supply to rise from 10% to 90% of its final value ? twait is the time delay between the end of the vdd_io ramp (90% of its final value) and the start of the vdd ramp figure 2. recommended power-up sequence symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 1.71 3.6 v vdd_io power supply for i/o 1.71 vdd + 0.1 v la_idd accelerometer current consumption in normal mode odr = 10 hz 60 a odr = 50 hz 160 odr ? 119 hz 330 g_idd gyroscope current consumption in normal mode 4.0 ma top operating temperature range -40 +85 c trise time for power supply rising (2) 0.01 100 ms twait time delay between vdd_io and vdd (2) 010ms 1. typical specifications are not guaranteed. 2. please refer to section 2.2.1: recommended power-up sequence for more details. trise twait trise 0v 0v vdd_io vdd
docid025604 rev 3 13/59 LSM6DS0 module specifications 59 2.3 temperature sensor characteristics @ vdd = 2.2 v, t = 25 c unless otherwise noted (b) b. the product is factory calibrated at 2.2 v. table 5. temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit todr temperature refresh rate gyro off (2) 50 hz gyro on 59.5 tsen temperature sensitivity (3) 16 lsb/c top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. when the accelerometer odr is set to 10 hz and the gyroscope part is turned off, the todr value is 10 hz. 3. the output of the temperature sensor is 0 (typ.) at 25 c
module specifications LSM6DS0 14/59 docid025604 rev 3 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. table 6. spi slave timing values symbol parameter value (1) unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 5 ns t h(cs) cs hold time 20 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 5 t dis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production
docid025604 rev 3 15/59 LSM6DS0 module specifications 59 2.4.2 i 2 c - inter-ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. sd a scl t su(sp) t w(scll) t su(sda) t su(sr) t h(st) t w(sclh) t h(sda) t w(sp:sr) start repea ted sta rt stop sta rt
module specifications LSM6DS0 16/59 docid025604 rev 3 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v t stg storage temperature range -40 to +125 c sg acceleration g for 0.1 ms 10,000 g esd electrostatic discharge protection (hbm) 2 kv vin input voltage on any control pin (including cs, scl/spc, sda/sdi/sdo, sdo/sa0) 0.3 to vdd_io +0.3 v this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part.
docid025604 rev 3 17/59 LSM6DS0 module specifications 59 2.6 terminology 2.6.1 sensitivity linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. an angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the considered axis. sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and time. 2.6.2 zero- g and zero rate level linear acceleration zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x-axis and y-axis, whereas the z-axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as two?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?linear acceleration zero- g level change vs. temperature? in table 3 . the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. the zero-rate level describes the actual output signal if there is no angular rate present. the zero-rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and time.
functionality LSM6DS0 18/59 docid025604 rev 3 3 functionality 3.1 operating modes the LSM6DS0 has two operating modes available: only accelerometer active and gyroscope in power-down or both accelerometer and gyroscope sensors active at the same odr. switching from one mode to the other requires one write operation: writing to ctrl_reg6_xl (20h) , the accelerometer operates in normal mode and the gyroscope is powered down, writing to ctrl_reg1_g (10h) both the accelerometer and gyroscope are activated at the same odr. figure 5 depicts both modes of operation from power down. figure 5. switching operating modes 3.2 gyroscope power modes in the LSM6DS0, the gyroscope can be configured in three different operating modes: power-down, low-power and normal mode. low-power mode is available for lower odr (14.9, 59.5, 119 hz) while for greater odr (238, 476, 952 hz) the device is automatically in normal mode. table 9 summarizes the odr configuration (odr_g[2:0] bits set in ctrl_reg1_g (10h) ) and the corresponding power modes. to enable low-power mode, the lp_mode bit in ctrl_reg3_g (12h) has to be set to ?1?. low-power mode allows reaching low-power consumption while maintaining the device always on, refer to table 10 . accelerometer only accelerometer + gyro power down write ctrl_reg1_g write ctrl_reg1_g with ctrl_reg6_xl = pd write ctrl_reg6_xl
docid025604 rev 3 19/59 LSM6DS0 functionality 59 table 9. gyroscope operating modes odr_g [2:0] odr [hz] power mode (1) 1. gyroscope low-power mode is available for g_fs = 2000 dps. 000 power-down power-down 001 14.9 low-power/normal mode 010 59.5 low-power/normal mode 011 119 low-power/normal mode 100 238 normal mode 101 476 normal mode 110 952 normal mode table 10. operating mode current consumption odr [hz] power mode current consumption (1) [ma] 1. typical values of gyroscope and accelerometer current consumption are based on characterization data 14.9 low-power 1.8 59.5 low-power 2.3 119 low-power 2.9 238 normal mode 4.3 476 normal mode 4.3 952 normal mode 4.3 table 11. accelerometer turn-on time odr [hz] bw = 400 hz (1) 1. the table contains the number of samples to be discarded after switching between power-down mode and normal mode. bw = 200 hz (1) bw = 100 hz (1) bw = 50 hz (1) 14.9 0 0 0 0 59.5 0 0 0 0 119 1 1 1 2 238 1 1 2 4 476 1 2 4 7 952 2 4 7 14
functionality LSM6DS0 20/59 docid025604 rev 3 3.3 multiple reads (burst) when only the accelerometer is activated and the gyroscope is in power down, starting from out_x_xl (28h - 29h) multiple reads can be performed. once out_z_xl (2ch - 2dh) is read, the system automatically restarts from out_x_xl (28h - 29h) (see figure 6 ). figure 6. multiple reads: accelerometer only when both accelerometer and gyroscope sensors are activated at the same odr, starting from out_x_g (18h - 19h) multiple reads can be performed. once out_z_xl (2ch - 2dh) is read, the system automatically restarts from out_x_g (18h - 19h) (see figure 7 ). figure 7. multiple reads: accelerometer and gyroscope table 12. gyroscope turn-on time odr [hz] lpf1 only (1) 1. the table contains the number of samples to be discarded after switching between low-power mode and normal mode. lpf1 and lpf2 (1) 14.9 2 lpf2 not available 59.5 or 119 3 13 238 4 14 476 5 15 952 8 18 x,y,z out_z_xl read #1 (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl x,y,z read #n out_z_xl (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl (15-16) out_temp x,y,z out_z_xl read #1 (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl x,y,z read #n out_z_g (1c-1d) (1a-1b) out_y_g (18-19) out_x_g out_z_xl (2c-2d) (2a-2b) out_y_xl (28-29) out_x_xl out_z_g (1c-1d) (1a-1b) out_y_g (18-19) out_x_g (15-16) out_temp
docid025604 rev 3 21/59 LSM6DS0 functionality 59 3.4 digital block diagram figure 8. digital block diagram adc lpf1 1 0 hp_en lpf2 hpf data reg interrupt generator i2c spi out_sel int_sel src registers cfg registers gyro fifo lpf1 adc 1 0 hpf hpis1 fds xl gyro lpf2 hr interrupt generator xl 0 0 1 1 xl xl xl gyro gyro gyro
functionality LSM6DS0 22/59 docid025604 rev 3 3.5 fifo the LSM6DS0 embeds 32 slots of 16-bit data fifo for each of the gyroscope?s three output channels, yaw, pitch and roll, and 16-bit data fifo for each of the accelerometer?s three output channels, x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work accordingly to five different modes: bypass mode, fifo-mode, continuous mode, continuous-to-fifo mode and bypass-to-continuous. each mode is selected by the fmode [2:0] bits in the fifo_ctrl (2eh) register. programmable fifo threshold status, fifo overrun events and the number of unread samples stored are available in the fifo_src (2fh) register and can be set to generate dedicated interrupts on the int pin using the int_ctrl (0ch) register. fifo_src (2fh) (fth) goes to '1' when the number of unread samples ( fifo_src (2fh) (fss5:0)) is greater than or equal to fth [4:0] in fifo_ctrl (2eh) . if fifo_ctrl (2eh) (fth[4:0]) is equal to 0, fifo_src (2fh) (fth) goes to ?0?. fifo_src (2fh) (ovrn) is equal to '1' if a fifo slot is overwritten. fifo_src (2fh) (fss [5:0]) contains stored data levels of unread samples. when fss [5:0] is equal to ?000000?, fifo is empty. when fss [5:0] is equal to ?100000?, fifo is full and the unread samples are 32. the fifo feature is enabled by writing '1' in ctrl_reg9 (23h) (fifo_en). to guarantee the correct acquisition of data during the switching into and out of fifo mode, the first sample acquired must be discarded. 3.5.1 bypass mode in bypass mode ( fifo_ctrl (2eh) (fmode [2:0]= 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo mode. as described in figure 9 , for each channel only the first address is used. when new data is available the old data is overwritten. figure 9. bypass mode x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty
docid025604 rev 3 23/59 LSM6DS0 functionality 59 3.5.2 fifo mode in fifo mode ( fifo_ctrl (2eh) (fmode [2:0] = 001) data from the output channels are stored in the fifo until it is overwritten. to reset fifo content, bypass mode should be selected by writing fifo_ctrl (2eh) (fmode [2:0]) to '000'. after this reset command, it is possible to restart fifo mode, writing fifo_ctrl (2eh) (fmode [2:0]) to '001'. the fifo buffer memorizes 32 levels of data, but the depth of the fifo can be resized by setting the stop_on_fth bit in ctrl_reg9 (23h) . if the stop_on_fth bit is set to '1', fifo depth is limited to fifo_ctrl (2eh) (fth [4:0]) + 1 data. a fifo threshold interrupt can be enabled (int_ovr bit in int_ctrl (0ch) ) in order to be raised when the fifo is filled to the level specified by the fth[4:0] bits of fifo_ctrl (2eh) . when a fifo threshold interrupt occurs, the first data has been overwritten and the fifo stops collecting data from the input channels. figure 10. fifo mode 3.5.3 continuous mode continuous mode ( fifo_ctrl (2eh) (fmode[2:0] = 110) provides a continuous fifo update: as new data arrives the older is discarded. a fifo threshold flag fifo_src (2fh) (fth) is asserted when the number of unread samples in fifo is greater than or equal to fifo_ctrl (2eh) (fth4:0). it is possible to route fifo_src (2fh) (fth) to the int pin by writing the int_fth bit to ?1? in register int_ctrl (0ch) . a full-flag interrupt can be enabled ( int_ctrl (0ch) (int_ fss5)= '1') when the fifo becomes saturated and in order to read the contents all at once. if an overrun occurs, the oldest sample in fifo is overwritten and the ovrn flag in fifo_src (2fh) is asserted. in order to empty the fifo before it is full, it is also possible to pull from fifo the number of unread samples available in fifo_src (2fh) (fss[5:0]). x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i
functionality LSM6DS0 24/59 docid025604 rev 3 figure 11. continuous mode 3.5.4 continuous-to-fifo mode in continuous-to-fifo mode ( fifo_ctrl (2eh) (fmode [2:0] = 011), fifo behavior changes according to the int_gen_src_xl (26h) (ia_xl) bit. when the int_gen_src_xl (26h) (ia_xl) bit is equal to '1', fifo operates in fifo mode. when the int_gen_src_xl (26h) (ia_xl) bit is equal to '0', fifo operates in continuous mode. the interrupt generator should be set to the desired configuration by means of int_gen_cfg_xl (06h) , int_gen_ths_x_xl (07h) , int_gen_ths_y_xl (08h) and int_gen_ths_z_xl (09h) . the ctrl_reg4 (1eh) (lir_xl) bit should be set to '1' in order to have latched interrupt. figure 12. continuous-to-fifo mode x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30 x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i continuous mode fifo mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30
docid025604 rev 3 25/59 LSM6DS0 functionality 59 3.5.5 bypass-to-continuous mode in bypass-to-continuous mode ( fifo_ctrl (2eh) (fmode[2:0] = '100'), data measurement storage inside fifo operates in continuous mode when int_gen_src_xl (26h) (ia_xl) is equal to '1', otherwise fifo content is reset (bypass mode). the interrupt generator should be set to the desired configuration by means of int_gen_cfg_xl (06h) , int_gen_ths_x_xl (07h) , int_gen_ths_y_xl (08h) and int_gen_ths_z_xl (09h) . the ctrl_reg4 (1eh) (lir_xl) bit should be set to '1' in order to have latched interrupt. figure 13. bypass-to-continuous mode x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty bypass mode continuous mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30
digital interfaces LSM6DS0 26/59 docid025604 rev 3 4 digital interfaces the registers embedded inside the LSM6DS0 may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e connected to vdd_io). 4.1 i 2 c serial interface the LSM6DS0 i 2 c is a bus slave. the i 2 c is employed to write the data to the registers whose content can also be read back. the relevant i 2 c terminology is provided in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines must be connected to vdd_io through an external pull- up resistor. when the bus is free, both the lines are high. the i 2 c interface is implemeted with fast mode (400 khz) i 2 c standards as well as with the standard mode. in order to disable the i 2 c block, the i2c_disable bit must be written to ?1? in ctrl_reg9 (23h) . table 13. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo/sa0 spi serial data output (sdo) i 2 c less significant bit of the device address table 14. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
docid025604 rev 3 27/59 LSM6DS0 digital interfaces 59 4.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LSM6DS0 is 110101xb. the sdo/sa0 pin can be used to modify the less significant bit of the device address. if the sdo/sa0 pin is connected to a voltage supply, lsb is ?1? (address 1101011b), else if the sdo/sa0 pin is connected to ground, the lsb value is ?0? (address 1101010b). this solution permits to connect and address two different inertial modules to the same i 2 c bus. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LSM6DS0 behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted. the increment of the address is configured by the ctrl_reg8 (22h) (if_add_inc). the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes. if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 15 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 15. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 110101 0 1 11010101 (d5h) write 110101 0 0 11010100 (d4h) read 110101 1 1 11010111 (d7h) write 110101 1 0 11010110 (d6h) table 16. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 17. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak
digital interfaces LSM6DS0 28/59 docid025604 rev 3 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 4.2 spi bus interface the LSM6DS0 spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface connects to applications using 4 wires: cs , spc , sdi and sdo . figure 14. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . table 18. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 19. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data dat a data cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7do6do5do4do3do2do1do0 ad6
docid025604 rev 3 29/59 LSM6DS0 digital interfaces 59 both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods will be added. when the ctrl_reg8 (22h) (if_add_inc) bit is ?0?, the address used to read/write data remains the same for every block. when the ctrl_reg8 (22h) (if_add_inc) bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 4.2.1 spi read figure 15. spi read protocol the spi read command is performed with 16 clock pulses. a multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ad6
digital interfaces LSM6DS0 30/59 docid025604 rev 3 figure 16. multiple byte spi read protocol (2-byte example) 4.2.2 spi write figure 17. spi write protocol the spi write command is performed with 16 clock pulses. a multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 -7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 18. multiple byte spi write protocol (2-byte example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ad6 cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ad6 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ad6
docid025604 rev 3 31/59 LSM6DS0 digital interfaces 59 4.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the ctrl_reg8 (22h) (sim) bit equal to ?1? (spi serial interface mode selection). figure 19. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ad6
application hints LSM6DS0 32/59 docid025604 rev 3 5 application hints figure 20. LSM6DS0 electrical connections 5.1 external capacitors the device core is supplied through the vdd line. power supply decoupling capacitors (c2, c3 = 100 nf ceramic, c4 = 10 f al) should be placed as near as possible to the supply pin of the device (common design practice). the functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the spi/i 2 c interface. 10nf(16v) *c1 gnd * c1 must guarantee 1 nf value under 11 v bias condition (top view) 1 5 vdd_io scl/spc sda /sdi/sdo sdo/sa0 cs res int res res res res gnd gnd vdd res cap 100 nf gnd gnd 10 f c3 c4 vdd gnd vdd_io gnd 100 nf c2 9 13
docid025604 rev 3 33/59 LSM6DS0 register mapping 59 6 register mapping the table given below provides a list of the 8/16 bit registers embedded in the device and the corresponding addresses. table 20. register mapping name type register address default note hex binary reserved -- 00-03 -- -- reserved act_ths r/w 04 00000100 00000000 act_dur r/w 05 00000101 00000000 int_gen_cfg_xl r/w 06 00000110 00000000 int_gen_ths_x_xl r/w 07 00000111 00000000 int_gen_ths_y_xl r/w 08 00001000 00000000 int_gen_ths_z_xl r/w 09 00001001 00000000 int_gen_dur_xl r/w 0a 00001010 00000000 reference_g r/w 0b 00001011 00000000 int_ctrl r/w 0c 00001100 00000000 reserved -- 0d-0e -- -- reserved who_am_i r 0f 00001111 01101000 ctrl_reg1_g r/w 10 00010000 00000000 ctrl_reg2_g r/w 11 00010001 00000000 ctrl_reg3_g r/w 12 00010010 00000000 orient_cfg_g r/w 13 00010011 00000000 int_gen_src_g r 14 00010100 output out_temp_l r 15 00010101 output out_temp_h r 16 00010110 output status_reg r 17 00010111 output out_x_l_g r 18 00011000 output out_x_h_g r 19 00011001 output out_y_l_g r 1a 00011010 output out_y_h_g r 1b 00011011 output out_z_l_g r 1c 00011100 output out_z_h_g r 1d 00011101 output ctrl_reg4 r/w 1e 00011110 00111000 ctrl_reg5_xl r/w 1f 0001 1111 0011 1000 ctrl_reg6_xl r/w 20 00100000 00000000
register mapping LSM6DS0 34/59 docid025604 rev 3 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. to guarantee proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored on those registers must not be changed. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. ctrl_reg7_xl r/w 21 00100001 00000000 ctrl_reg8 r/w 22 00100010 00000100 ctrl_reg9 r/w 23 00100011 00000000 ctrl_reg10 r/w 24 00100100 00000000 reserved -- 25 -- -- reserved int_gen_src_xl r 26 00100110 output status_reg r 27 00100111 output out_x_l_xl r 28 00101000 output out_x_h_xl r 29 00101001 output out_y_l_xl r 2a 00101010 output out_y_h_xl r 2b 00101011 output out_z_l_xl r 2c 00101100 output out_z_h_xl r 2d 00101101 output fifo_ctrl r/w 2e 00101110 00000000 fifo_src r 2f 00101111 output int_gen_cfg_g r/w 30 00110000 00000000 int_gen_ths_xh_g r/w 31 00110001 00000000 int_gen_ths_xl_g r/w 32 00110010 00000000 int_gen_ths_yh_g r/w 33 00110011 00000000 int_gen_ths_yl_g r/w 34 00110100 00000000 int_gen_ths_zh_g r/w 35 00110101 00000000 int_gen_ths_zl_g r/w 36 00110110 00000000 int_gen_dur_g r/w 37 00110111 00000000 reserved r 38-7f -- -- reserved table 20. register mapping (continued) name type register address default note hex binary
docid025604 rev 3 35/59 LSM6DS0 register description 59 7 register description the device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. the register addresses, consisting of 7 bits, are used to identify them and to write the data through the serial interface. 7.1 act_ths (04h) activity threshold register. table 22. act_ths register description 7.2 act_dur (05h) inactivity duration register. table 24. act_dur register description 7.3 int_gen_cfg_xl (06h) linear acceleration sensor interrupt generator configuration register. table 21. act_ths register sleep_on _inact_en act_ths6 act_ths5 act_ths4 act_ths3 act_ths2 act_ths1 act_ths0 sleep_on_ inact_en gyroscope operating mode during inactivity. default value: 0 (0: gyroscope in power-down; 1: gyroscope in sleep mode) act_ths [6:0] inactivity threshold. default value: 000 0000 table 23. act_dur register act_dur7 act_dur6 act_dur5 act_dur4 act_dur3 act_dur2 act_dur1 act_dur0 act_dur [7:0] inactivity duration. default value: 0000 0000 table 25. int_gen_cfg_xl register aoi_xl 6d zhie_xl zlie_xl yhie_xl ylie_xl xhie_xl xlie_xl
register description LSM6DS0 36/59 docid025604 rev 3 table 26. int_gen_cfg_xl register description 7.4 int_gen_ths_x_xl (07h) linear acceleration sensor interrupt threshold register. table 28. int_gen_ths_x_xl register description aoi_xl and/or combination of accelerometer?s interrupt events. default value: 0 (0: or combination; 1: and combination) 6d 6-direction detection function for interrupt. default value: 0 (0: disabled; 1: enabled) zhie_xl enable interrupt generation on accelerometer?s z-axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) zlie_xl enable interrupt generation on accelerometer?s z-axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) yhie_xl enable interrupt generation on accelerometer?s y-axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) ylie_xl enable interrupt generation on accelerometer?s y-axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) xhie_xl enable interrupt generation on accelerometer?s x-axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) xlie_xl enable interrupt generation on accelerometer?s x-axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) table 27. int_gen_ths_x_xl register ths_xl_x7 ths_xl_x6 ths_xl_x5 ths_xl_x4 ths_xl_x3 ths_xl_x2 ths_xl_x1 ths_xl_x0 ths_xl_x [7:0] x-axis interrupt threshold. default value: 0000 0000
docid025604 rev 3 37/59 LSM6DS0 register description 59 7.5 int_gen_ths_y_xl (08h) linear acceleration sensor interrupt threshold register. table 30. int_gen_ths_y_xl register description 7.6 int_gen_ths_z_xl (09h) linear acceleration sensor interrupt threshold register. table 32. int_gen_ths_z_xl register description 7.7 int_gen_dur_xl (0ah) linear acceleration sensor interrupt duration register. table 33. int_gen_dur_xl register table 34. int_gen_dur_xl register description 7.8 reference_g (0bh) angular rate sensor reference value register for digital high-pass filter (r/w) table 35. reference_g register table 36. reference_g register description table 29. int_gen_ths_y_xl register ths_xl_y7 ths_xl_y6 ths_xl_y5 ths_xl_y4 ths_xl_y3 ths_xl_y2 ths_xl_y1 ths_xl_y0 ths_xl_y [7:0] y-axis interrupt threshold. default value: 0000 0000 table 31. int_gen_ths_z_xl register ths_xl_z7 ths_xl_z6 ths_xl_z5 ths_xl_z4 ths_xl_z3 ths_xl_z2 ths_xl_z1 ths_xl_z0 ths_xl_z [7:0] z-axis interrupt threshold. default value: 0000 0000 wait_xl dur_xl6 dur_xl5 dur_xl4 dur_xl3 dur_xl2 dur_xl1 dur_xl0 wait_xl wait function enabled on duration counter. default value: 0 (0: wait function off; 1: wait for dur_xl [6:0] samples before exiting interrupt) dur_xl [6:0] enter/exit interrupt duration value. default value: 000 0000 ref7_g ref6_g ref5_g ref4_g ref3_g ref2_g ref1_g ref0_g ref_g [7:0] reference value for gyroscope?s digital high-pass filter (r/w). default value: 0000 0000
register description LSM6DS0 38/59 docid025604 rev 3 7.9 int_ctrl (0ch) int pin control register. table 37. int_ctrl register table 38. int_ctrl register description 7.10 who_am_i (0fh) who_am_i register. 7.11 ctrl_reg1_g (10h) angular rate sensor control register 1. table 40. ctrl_reg1_g register int_ig _g int_ig_xl int_ fss5 int_ovr int_fth int_ boot int_ drdy_g int_ drdy_xl int_ig_g gyroscope interrupt enable on int pin. default value: 0 (0: disabled; 1: enabled) int_ ig_xl accelerometer interrupt generator on int pin. default value: 0 (0: disabled; 1: enabled) int_ fss5 fss5 interrupt enable on int pin. default value: 0 (0: disabled; 1: enabled) int_ovr overrun interrupt on int pin. default value: 0 (0: disabled; 1: enabled) int_fth fifo threshold interrupt on int pin. default value: 0 (0: disabled; 1: enabled) int_ boot boot status available on int pin. default value: 0 (0: disabled; 1: enabled) int_drdy_g gyroscope data ready on int pin. default value: 0 (0: disabled; 1: enabled) int_drdy_xl accelerometer data ready on int pin. default value: 0 (0: disabled; 1: enabled) table 39. who_am_i register 01101000 odr_g2 odr_g1 odr_g0 fs_g1 fs_g0 0 (1) bw_g1 bw_g0 1. this bit must be set to ?0? for the correct operation of the device
docid025604 rev 3 39/59 LSM6DS0 register description 59 table 41. ctrl_reg1_g register description odr_g [2:0] are used to set odr selection when both the accelerometer and gyroscope are activated. bw_g [1:0] are used to set the bandwidth selection of the gyroscope. the following table summarizes all frequencies available for each combination of the odr_g / bw_g bits after lpf1 (see table 42 ) and lpf2 (see table 43 ) when both the accelerometer and gyroscope are activated. for more details regarding signal processing please refer to figure 21 . odr_g [2:0] gyroscope output data rate selection . default value: 000 (refer to table 42 and table 43 ) fs_g [1:0] gyroscope full-scale selection. default value: 00 (00: 245 dps; 01: 500 dps; 10: not available; 11: 2000 dps) bw_g [1:0] gyroscope bandwidth selection. default value: 00 table 42. odr and bw configuration setting (after lpf1) odr_g2 odr_g1 odr_g0 odr [hz] cutoff [hz] (1) 1. the values in the table are indicative and can vary proportionally with the specific odr value. 0 0 0 power-down n.a. 0 0 1 14.9 5 0 1 0 59.5 19 0 1 1 119 38 1 0 0 238 76 1 0 1 476 100 1 1 0 952 100 1 1 1 n.a. n.a.
register description LSM6DS0 40/59 docid025604 rev 3 table 43. odr and bw configuration setting (after lpf2) odr_g [2:0] bw_g [1:0] odr [hz] cutoff [hz] (1) 1. the values in the table are indicative and can vary proportionally with the specific odr value. 000 00 power-down n.a. 000 01 power-down n.a. 000 10 power-down n.a. 000 11 power-down n.a. 001 00 14.9 n.a. 001 01 14.9 n.a. 001 10 14.9 n.a. 001 11 14.9 n.a. 010 00 59.5 16 010 01 59.5 16 010 10 59.5 16 010 11 59.5 16 011 00 119 14 011 01 119 31 011 10 119 31 011 11 119 31 100 00 238 14 100 01 238 29 100 10 238 63 100 11 238 78 101 00 476 21 101 01 476 28 101 10 476 57 101 11 476 100 110 00 952 33 110 01 952 40 110 10 952 58 110 11 952 100 111 00 n.a. n.a. 111 01 n.a. n.a. 111 10 n.a. n.a. 111 11 n.a. n.a.
docid025604 rev 3 41/59 LSM6DS0 register description 59 7.12 ctrl_reg2_g (11h) angular rate sensor control register 2. figure 21. int_sel and out_sel configuration gyroscope block diagram 7.13 ctrl_reg3_g (12h) angular rate sensor control register 3. table 44. ctrl_reg2_g register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) 0 (1) int_sel1 int_sel0 out_sel1 out_sel0 table 45. ctrl_reg2_g register description int_sel [1:0] int selection configuration. default value: 00 (refer to figure 21 ) out_sel [1:0] out selection configuration. default value: 00 (refer to figure 21 ) adc lpf1 hpf lpf2 datareg fifo interrupt generator table 46. ctrl_reg3_g register lp_mode hp_en 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) hpcf3_g hpcf2_g hpcf1_g hpcf0_g table 47. ctrl_reg3_g register description lp_mode low-power mode enable. default value: 0 (0: low-power disable; 1: low-power enable) hp_en high-pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled, refer to figure 21 ) hpcf_g [3:0] gyroscope high-pass filter cutoff frequency selection. default value: 0000 refer to table 48 .
register description LSM6DS0 42/59 docid025604 rev 3 7.14 orient_cfg_g (13h) angular rate sensor sign and orientation register. table 49. orient_cfg_g register table 50. orient_cfg_g register description table 48. gyroscope high-pass filter cutoff frequency configuration [hz] (1) hpcf_g [3:0] odr= 14.9 hz odr= 59.5 hz odr= 119 hz odr= 238 hz odr= 476 hz odr= 952 hz 0000 1 4 8 15 30 57 0001 0.5 2 4 8 15 30 0010 0.2 1 2 4 8 15 0011 0.1 0.5 1 2 4 8 0100 0.05 0.2 0.5 1 2 4 0101 0.02 0.1 0.2 0.5 1 2 0110 0.01 0.05 0.1 0.2 0.5 1 0111 0.005 0.02 0.05 0.1 0.2 0.5 1000 0.002 0.01 0.02 0.05 0.1 0.2 1001 0.001 0.005 0.01 0.02 0.05 0.1 1. values in the table are indicative and can vary proportionally with the specific odr value. 0 (1) 0 (1) signx_g signy_g signz_g orient_2 orient_1 orient_0 1. these bits must be set to ?0? for the correct operation of the device signx_g pitch axis (x) angular rate sign. default value: 0 (0: positive sign; 1: negative sign) signy_g roll axis (y) angular rate sign. default value: 0. (0: positive sign; 1: negative sign) signz_g yaw axis (z) angular rate sign. default value: 0. (0: positive sign; 1: negative sign) orient [2:0] directional user orientation selection. default value: 000
docid025604 rev 3 43/59 LSM6DS0 register description 59 7.15 int_gen_src_g (14h) angular rate sensor interrupt source register. 7.16 out_temp_l (15h), out_temp_h (16h) temperature data output register. l and h registers together express a 16-bit word in two?s complement right-justified. table 51. int_gen_src_g register 0 ia_g zh_g zl_g yh_g yl_g xh_g xl_g table 52. int_gen_src_g register description ia_g interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh_g yaw (z) high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl_g yaw (z) low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh_g roll (y) high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl_g roll (y) low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh_g pitch (x) high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl_g pitch (x) low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 53. out_temp_l register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 54. out_temp_h register temp11 temp11 temp11 temp11 temp11 temp10 temp9 temp8 table 55. out_temp register description temp [11:0] temperature sensor output data. the value is expressed as two?s complement sign extended to the msb.
register description LSM6DS0 44/59 docid025604 rev 3 7.17 status_reg (17h) status register. 7.18 out_x_g (18h - 19h) angular rate sensor pitch axis (x) angular rate output register. the value is expressed as a 16-bit word in two?s complement. 7.19 out_y_g (1ah - 1bh) angular rate sensor roll axis (y) angular rate output register. the value is expressed as a 16-bit word in two?s complement. 7.20 out_z_g (1ch - 1dh) angular rate sensor yaw axis (z) angular rate output register. the value is expressed as a 16-bit word in two?s complement. table 56. status_reg register 0 ig_xl ig_g inact boot_ status tda gda xlda table 57. status_reg register description ig_xl accelerometer interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ig_g gyroscope interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) inact inactivity interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) boot_ status boot running flag signal. default value: 0 (0: no boot running; 1: boot running) tda temperature sensor new data available. default value: 0 (0: new data is not yet available; 1: new data is available) gda gyroscope new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) xlda accelerometer new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available)
docid025604 rev 3 45/59 LSM6DS0 register description 59 7.21 ctrl_reg4 (1eh) control register 4. 7.22 ctrl_reg5_xl (1fh) linear acceleration sensor control register 5. table 58. ctrl_reg4 register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) zen_g yen_g xen_g 0 (1) lir_xl1 4d_xl1 table 59. ctrl_reg4 register description zen_g gyroscope?s yaw axis (z) output enable. default value: 1 (0: z-axis output disabled; 1: z-axis output enabled) yen_g gyroscope?s roll axis (y) output enable. default value: 1 (0: y-axis output disabled; 1: y-axis output enabled) xen_g gyroscope?s pitch axis (x) output enable. default value: 1 (0: x-axis output disabled; 1: x-axis output enabled) lir_xl1 latched interrupt. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) 4d_xl1 4d option enabled on interrupt. default value: 0 (0: interrupt generator uses 6d for position recognition; 1: interrupt generator uses 4d for position recognition) table 60. ctrl_reg5_xl register dec_1 dec_0 zen_xl yen_xl xen_xl 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) table 61. ctrl_reg5_xl register description dec_ [0:1] decimation of acceleration data on out reg and fifo. default value: 00 (00: no decimation; 01: update every 2 samples; 10: update every 4 samples; 11: update every 8 samples) zen_xl accelerometer?s z-axis output enable. default value: 1 (0: z-axis output disabled; 1: z-axis output enabled) yen_xl accelerometer?s y-axis output enable. default value: 1 (0: y-axis output disabled; 1: y-axis output enabled) xen_xl accelerometer?s x-axis output enable. default value: 1 (0: x-axis output disabled; 1: x-axis output enabled)
register description LSM6DS0 46/59 docid025604 rev 3 7.23 ctrl_reg6_xl (20h) linear acceleration sensor control register 6. table 62. ctrl_reg6_xl register table 63. ctrl_reg6_xl register description odr_xl [2:0] is used to set the power mode and odr selection. table 64 summarizes all available frequencies when only the accelerometer is activated. odr_xl2 odr_xl1 odr_xl0 fs1_xl fs0_xl bw_scal _odr bw_xl1 bw_xl0 odr_xl [2:0] output data rate and power mode selection . default value: 000 (see table 67 ) fs_xl [1:0] accelerometer full-scale selection. default value: 00 (00: 2 g ; 01: 16 g ; 10: 4 g ; 11: 8 g ) bw_scal_odr bandwidth selection. default value: 0 (0: bandwidth determined by odr selection: - bw = 408 hz when odr = 952 hz, 50 hz, 10 hz; - bw = 211 hz when odr = 476 hz; - bw = 105 hz when odr = 238 hz; - bw = 50 hz when odr = 119 hz; 1: bandwidth selected according to bw_xl [2:1] selection) bw_xl [1:0] anti-aliasing filter bandwidth selection. default value: 00 (00: 408 hz; 01: 211 hz; 10: 105 hz; 11: 50 hz) table 64. odr register setting (accelerometer only mode) odr_xl2 odr_xl1 odr_xl0 odr selection [hz] 0 0 0 power-down 0 0 1 10 hz 0 1 0 50 hz 0 1 1 119 hz 1 0 0 238 hz 1 0 1 476 hz 1 1 0 952 hz 1 1 1 n.a.
docid025604 rev 3 47/59 LSM6DS0 register description 59 7.24 ctrl_reg7_xl (21h) linear acceleration sensor control register 7. 7.25 ctrl_reg8 (22h) control register 8. table 65. ctrl_reg7_xl register hr dcf1 dcf0 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) fds 0 (1) hpis1 table 66. ctrl_reg7_xl register description hr high resolution mode for accelerometer enable. default value: 0 (0: disabled; 1: enabled). refer to table 67 . dcf[1:0] accelerometer digital filter (high-pass and low-pass) cutoff frequency selection: the band- width of the high-pass filter depends on the selected odr. refer to table 67 . fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) hpis1 high-pass filter enabled for acceleration sensor interrupt function on interrupt. default value: 0 (0: filter bypassed; 1: filter enabled) table 67. low pass cut-off frequency in high resolution mode (hr = 1) hr ctrl_reg7 (dcf [1:0]) lp cutoff freq. [hz] 1 00 odr/50 1 01 odr/100 1 10 odr/9 1 11 odr/400 table 68. ctrl_reg8 register boot bdu h_lactive pp_od sim if_add_inc ble sw_reset
register description LSM6DS0 48/59 docid025604 rev 3 7.26 ctrl_reg9 (23h) control register 9. table 69. ctrl_reg8 register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content (1) ) 1. boot request is executed as soon as the internal oscillator is turned-on. it is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode or sleep mode. bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb read) h_lactive interrupt activation level. default value: 0 (0: interrupt output pins active high; 1: interrupt output pins active low) pp_od push-pull/open drain selection on int pin. default value: 0 (0: push-pull mode; 1: open drain mode) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). if_add_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). default value: 1 (0: disabled; 1: enabled) ble big/little endian data selection. default value 0 (0: data lsb @ lower address; 1: data msb @ lower address) sw_reset software reset. default value: 0 (0: normal mode; 1: reset device) table 70. ctrl_reg9 register 0 (1) 1. these bits must be set to ?0? for the correct operation of the device sleep_g 0 (1) fifo_ temp_en drdy_ mask_bit i2c_disable fifo_en stop_on _fth table 71. ctrl_reg9 register description sleep_g gyroscope sleep mode enable. default value: 0 (0: disabled; 1: enabled) fifo_temp_en temperature data storage in fifo enable. default value: 0 (0: temperature data not stored in fifo; 1: temperature data stored in fifo) drdy_mask_bit data available enable bit. default value: 0 (0: da timer disabled; 1: da timer enabled) i2c_disable disable i 2 c interface. default value: 0. (0: both i 2 c and spi enabled; 1: i 2 c disabled, spi only) fifo_en fifo memory enable. default value: 0 (0: disabled; 1: enabled) stop_on_fth enable fifo threshold level use. default value: 0. (0: fifo depth is not limited; 1: fifo depth is limited to threshold level)
docid025604 rev 3 49/59 LSM6DS0 register description 59 7.27 ctrl_reg10 (24h) control register 10. table 72. ctrl_reg10 register table 73. ctrl_reg10 register description 7.28 int_gen_src_xl (26h) linear acceleration sensor interrupt source register. 0 (1) 1. these bits must be set to ?0? for the correct operation of the device 0 (1) 0 (1) 0 (1) 0 (1) st_g 0 (1) st_xl st_g angular rate sensor self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled) st_xl linear acceleration sensor self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled) table 74. int_gen_src_xl register 0 ia_xl zh_xl zl_xl yh_xl yl_xl xh_xl xl_xl table 75. int_gen_src_xl register description ia_xl interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh_xl accelerometer?s z high event. default value: 0 (0: no interrupt, 1: z high event has occurred) zl_xl accelerometer?s z low event. default value: 0 (0: no interrupt; 1: z low event has occurred) yh_xl accelerometer?s y high event. default value: 0 (0: no interrupt, 1: y high event has occurred) yl_xl accelerometer?s y low event. default value: 0 (0: no interrupt, 1: y low event has occurred) xh_xl accelerometer?s x high event. default value: 0 (0: no interrupt, 1: x high event has occurred) xl_xl accelerometer?s x low event. default value: 0 (0: no interrupt, 1: x low event has occurred)
register description LSM6DS0 50/59 docid025604 rev 3 7.29 status_reg (27h) status register. 7.30 out_x_xl (28h - 29h) linear acceleration sensor x-axis output register. the value is expressed as a 16-bit word in two?s complement. 7.31 out_y_xl (2ah - 2bh) linear acceleration sensor y-axis output register. the value is expressed as a 16-bit word in two?s complement. 7.32 out_z_xl (2ch - 2dh) linear acceleration sensor z-axis output register. the value is expressed as a 16-bit word in two?s complement. table 76. status_reg register 0 ig_xl ig_g inact boot_ status tda gda xlda table 77. status_reg register description ig_xl accelerometer interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ig_g gyroscope interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) inact inactivity interrupt output signal. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) boot_ status boot running flag signal. default value: 0 (0: no boot running; 1: boot running) tda temperature sensor new data available. default value: 0 (0: new data is not yet available; 1: new data is available) gda gyroscope new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) xlda accelerometer new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available)
docid025604 rev 3 51/59 LSM6DS0 register description 59 7.33 fifo_ctrl (2eh) fifo control register. 7.34 fifo_src (2fh) fifo status control register. table 81. fifo_src register table 82. fifo_src register description table 78. fifo_ctrl register fmode2 fmode1 fmode0 fth4 fth3 fth2 fth1 fth0 table 79. fifo_ctrl register description fmode [2:0] fifo mode selection bits. default value: 000 for further details refer to table 80 . fth [4:0] fifo threshold level setting. default value: 0 0000 table 80. fifo mode selection fmode2 fmode1 fmode0 mode 0 0 0 bypass mode. fifo turned off 0 0 1 fifo mode. stop collecting data when fifo is full. 0 1 0 reserved 0 1 1 continuous mode until trigger is deasserted, then fifo mode. 1 0 0 bypass mode until trigger is deasserted, then continuous mode. 1 1 0 continuous mode. if the fifo is full, the new sample over- writes the older sample. fth ovrn fss5 fss4 fss3 fss2 fss1 fss0 fth fifo threshold status. (0: fifo filling is lower than threshold level; 1: fifo filling is equal to or higher than the threshold level ovrn fifo overrun status. (0: fifo is not completely filled; 1: fifo is completely filled and at least one sample has been overwritten) for further details refer to table 83 . fss [5:0] number of unread samples stored in fifo. (000000: fifo empty; 100000: fifo full, 32 unread samples) for further details refer to table 83 .
register description LSM6DS0 52/59 docid025604 rev 3 7.35 int_gen_cfg_g (30h) angular rate sensor interrupt generator configuration register. table 85. int_gen_cfg_g register description table 83. fifo_src example: ovr/fss details fth ovrn fss5 fss4 fss3 fss2 fss1 fss0 description 00000000 fifo empty -- (1) 1. when the number of unread samples in fifo is greater than the threshold level set in register fifo_ctrl (2eh) , the fth value is ?1?. 00000011 unread sample ... -- (1) 010000032 unread sample 11100000at least one sample has been overwritten table 84. int_gen_cfg_g register aoi_g lir_g zhie_g zlie_g yhie_g ylie_g xhie_g xlie_g aoi_g and/or combination of gyroscope?s interrupt events. default value: 0 (0: or combination; 1: and combination) lir_g latch gyroscope interrupt request. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) zhie_g enable interrupt generation on gyroscope?s yaw (z) axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) zlie_g enable interrupt generation on gyroscope?s yaw (z) axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) yhie_g enable interrupt generation on gyroscope?s roll (y) axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) ylie_g enable interrupt generation on gyroscope?s roll (y) axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) xhie_g enable interrupt generation on gyroscope?s pitch (x) axis high event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) xlie_g enable interrupt generation on gyroscope?s pitch (x) axis low event. default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold)
docid025604 rev 3 53/59 LSM6DS0 register description 59 7.36 int_gen_ths_x_g (31h - 32h) angular rate sensor interrupt generator threshold registers. the value is expressed as a 15- bit word in two?s complement. table 88. int_gen_ths_x_g register description 7.37 int_gen_ths_y_g (33h - 34h) angular rate sensor interrupt generator threshold registers. the value is expressed as a 15- bit word in two?s complement. table 91. int_gen_ths_y_g register description table 86. int_gen_ths_xh_g register dcrm_g ths_g_ x14 ths_g_ x13 ths_g_ x12 ths_g_ x11 ths_g_ x10 ths_g_ x9 ths_g_ x8 table 87. int_gen_ths_xl_g register ths_g_ x7 ths_g_ x6 ths_g_ x5 ths_g_ x4 ths_g_ x3 ths_g_ x2 ths_g_ x1 ths_g_ x0 dcrm_g decrement or reset counter mode selection. default value: 0 (0: reset; 1: decrement, as per counter behavior in figure 22 and figure 23 ) ths_g_x [14:0] angular rate sensor interrupt threshold on pitch (x) axis. default value: 0000000 00000000 table 89. int_gen_ths_yh_g register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device ths_g_ y14 ths_g_ y13 ths_g_ y12 ths_g_ y11 ths_g_ y10 ths_g_ y9 ths_g_ y8 table 90. int_gen_ths_yl_g register ths_g_ y7 ths_g_ y6 ths_g_ y5 ths_g_ y4 ths_g_ y3 ths_g_ y2 ths_g_ y1 ths_g_ y0 ths_g_y [14:0] angular rate sensor interrupt threshold on roll (y) axis . default value: 0000000 00000000
register description LSM6DS0 54/59 docid025604 rev 3 7.38 int_gen_ths_z_g (35h - 36h) angular rate sensor interrupt generator threshold registers. the value is expressed as 15bit word in two?s complement. table 94. int_gen_ths_z_g register description 7.39 int_gen_dur_g (37h) angular rate sensor interrupt generator duration register. table 95. int_gen_dur_g register table 96. int_gen_dur_g register description the dur_g [6:0] bits set the minimum duration of the interrupt event to be recognized. duration steps and maximum values depend on the odr chosen. the wait_g bit has the following meaning: ?0?: the interrupt falls immediately if the signal crosses the selected threshold ?1?: if the signal crosses the selected threshold, the interrupt falls after a number of samples equal to the value of the duration counter register. for further details refer to figure 22 and figure 23 . table 92. int_gen_ths_zh_g register 0 (1) 1. this bit must be set to ?0? for the correct operation of the device ths_g_ z14 ths_g_ z13 ths_g_ z12 ths_g_ z11 ths_g_ z10 ths_g_ z9 ths_g_ z8 table 93. int_gen_ths_zl_g register ths_g_ z7 ths_g_ z6 ths_g_ z5 ths_g_ z4 ths_g_ z3 ths_g_ z2 ths_g_ z1 ths_g_ z0 ths_g_z [14:0] angular rate sensor interrupt thresholds on yaw (z) axis. default value: 0000000 00000000 wait_g dur_g6 dur_g5 dur_g4 dur_g3 dur_g2 dur_g1 dur_g0 wait_g exit from interrupt wait function enable. default value: 0 (0: wait function off; 1: wait for dur_g [6:0] samples before exiting interrupt) dur_g [6:0] enter/exit interrupt duration value. default value: 000 0000
docid025604 rev 3 55/59 LSM6DS0 register description 59 figure 22. wait bit disabled figure 23. wait bit enabled ? wait bit = ?0? interrupt disabled as soon as condition is no longer valid (ex: ra te value below threshold) rate (dps) rate threshold 0 t(n) t(n) t(n) interrupt counter duration value ?wait? disabled ? wait bit = ?1? interrupt disabled after duration sample (sort of hysteresis) rate (dps) rate threshold 0 t(n) t(n) t(n) interrupt counter duration value ?wait? enabled duration value is the same used to validate interrupt
soldering information LSM6DS0 56/59 docid025604 rev 3 8 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www .st.com/mems .
docid025604 rev 3 57/59 LSM6DS0 package information 59 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 24. lga 3x3x0.86 16l package outline and dimensions dimensions are in millimeter unless otherwise specified general tolerance is +/-0.1mm unless otherwise specified outer dimensions item dimension [mm] tolerance [mm] 1 . 0 0 0 . 3 ] l [ h t g n e l 1 . 0 0 0 . 3 ] w [ h t d i w x a m 6 8 . 0 ] h [ t h g i e h
revision history LSM6DS0 58/59 docid025604 rev 3 10 revision history table 97. document revision history date revision changes 28-nov-2013 1 initial release 31-mar-2014 2 updated vdd to 2.2 v in section 2: module specifications updated sw_reset bit in table 69: ctrl_reg8 register description updated dimensions and revised package presentation in section 9: package information 03-nov-2014 3 document status promoted from preliminary to production data added 16 g linear acceleration full scale throughout datasheet updated footnote 2 of table 2: pin description updated figure 20: LSM6DS0 electrical connections
docid025604 rev 3 59/59 LSM6DS0 59 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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